1. Field of the Invention
The present invention relates to a semiconductor test system, a semiconductor test method, and a medium for recording a semiconductor test program used for the same system and method. More specifically, the present invention relates to a tester used in a test process for semiconductor devices each provided with a redundant circuit, and more particularly to a redundancy processor for deciding whether a device can be replaced with a redundant circuit provided for the device or not on the basis of fail data of the device to be measured, a redundancy processing method therefor and a medium for recording a redundancy processing program therefor.
2. Description of the Prior Art
In the conventional test process for a wafer on which ICs, LSIs, etc. each provided with a redundancy circuit are formed, in general a redundancy processing is executed to decide whether the defective positions of the wafer can be remedied or not.
In the above-mentioned wafer test process, an LSI tester is usually used. Here, the LSI tester has a buffer memory, and the defective data or fail data obtained when each device is tested are stored in this buffer memory. Therefore, on the basis of these stored fail data, it is possible to decide whether the device can be replaced with a redundancy circuit provided for each device or not.
Recently, however, the time required for the test and remedy decision processing has been increased more and more with increasing device capacity and increasing complexity of the redundant circuit. To overcome this problem, therefore, the LSI tester is generally provided with a dedicated redundancy processor used for only the remedy decision processing. In this case, it is possible to shorten the apparent time required for the test system processing, by executing the parallel processing of both the device test and the remedy decision processing at the same time.
FIG. 14 is a schematic block diagram showing an example of prior art test system composed of a tester 1 and a redundancy processor 2.
The tester 1 is composed of a controller 1a, a test section 1b, and a buffer memory 1c for storing the fail data. In the practical test, a device to be measured (e.g., IC, LSI, etc.) is set to the test section 1b, to store the fail data of the set device in the buffer memory 1c under control of the controller 1a. Here, for instance, the fail data are data indicative of whether memory cells are normal or abnormal at the respective rows and columns, respectively.
The redundancy processor 2 is composed of a buffer memory 2a for storing the fail addresses and a controller 2b. The controller 2b controls the total operation of the redundancy processor 2. Here, the buffer memory 2a stores fail addresses on the basis of the fail data transferred from the buffer memory 1c of the tester 1. In this case, the redundancy processor 2 stores only the fail addresses in the buffer memory 2a, to execute the remedy decision processing on the basis of these stored data. Here, although the necessary capacity of the buffer memory 2a can be decided on the basis of the number of the fail addresses to be stored, in general this number of the fail addresses increases with increasing capacity of the device to be measured. Therefore, there so far exists a problem in that the cost of the tester increases with increasing capacity of the buffer memory 2a, and further the throughput of the tester decreases with increasing time required to read the fail addresses.
FIG. 15 is a diagram showing the operation of the test system. As shown in FIG. 15, by the tester 1, a function test (1) of the device (e.g., IC, LSI, etc.) set to the test section 1b for test is executed by the controller 1a, so that the predetermined fail data can be stored in the buffer memory 1c. Further, when a function test (2) is being executed, the fail data obtained by the first function test (1) and stored in the buffer memory 1c are transferred to the redundancy processor 2. In the redundancy processor 2, the remedy processing (1) such as the remedy decision, the replacement with the spares, etc. is executed in cooperation with the buffer memory 2a. In the same way as above, the other function tests (3) to (n) are executed by the tester 1, and the other remedy processing (3) to (n) are executed by the redundancy processor in sequence.
FIGS. 16(a) and 16(b) are data construction tables of the fail data of the prior art tester (i.e., the buffer memory 1c) and the redundancy processor (i.e., the buffer memory 2a), respectively. In these drawing, the memory or, having 64 addresses in total (i.e., the row and column addresses are both eight) is shown by way of example. Further, the number of spares is assumed to be two in both the row and column, respectively. Here, the assumption is made that the fail data as shown by a mark [*] in FIG. 16(a) are stored in the buffer memory 1c of the tester 1. Therefore, when these fail data are transferred to the buffer memory 2a of the redundancy processor 2, all the fail addresses are stored in the buffer memory 2a. In this example, as shown by the actual data stored in FIG. 16(b), the addresses of 14 in total are stored on the basis of the numbers of the row and column, respectively.
FIG. 17 is a flowchart for assistance in explaining the remedy decision processing by the prior art redundancy processor.
First, in Step (S01), data are transferred from the tester (1) to the redundancy processor 2, that is, from the buffer memory (fail data) 1c to the buffer memory (fail address) 2a. After that, in Step (S02), the number of the fail addresses is checked as to whether exceeding the maximum number of the remediable addresses. Here, the maximum number of the remediable addresses can be obtained by the following formula: ##EQU1##
For instance, in the case of the example shown in FIGS. 16(a) and 16(b), the maximum remediable number is 32=(8.times.2)+(8.times.2). Therefore, when the number of the fail addresses exceeds this maximum remediable number, in Step (S08), the remedy is decided to be impossible.
Successively, in Step (S03), on the basis of the fail addresses stored in the buffer memory 2a, the line fail is detected, and spares are allocated to the detected line fail for remedy processing.
Here, "line fail" is defined as follows: when the replaced row spares or the replaced column spares are allocated to the fail addresses, since the number of fails at the same address (i.e., on the same line) is too many, the whole line replacement is indispensable. Further, the fail addresses other than the "line fail" are referred to as "bit fails", for discrimination between the two. Here, the conditions that the "line fail" is decided are that the number of fails on the same row address exceeds the number of column spares in the case of the row addresses and that the number of fails on the same column address exceeds the number of row spares in the case of the column addresses.
Further, when either one of the numbers of the row line fails or the column line fails exceeds the number of the row or column spares, in Step (S04), the remedy is decided to be impossible.
Finally, in Step (S05), the remedy processing is executed by allocating the remaining usable spares to the bit fails. In this case, in general the remedy processing is executed on the basis of all the combinations of the remaining spares. Further, when the actual remedy can be executed in Step (S06), the device remedy is decided as being possible in Step (S07).
However, recently, there exists such a tendency that the number of the spares increases with increasing capacity of the memory device. Therefore, in the case of the prior art test system, since the remedy decision of the bit fails is executed by allocating all the usable spares to all the fail addresses on the basis of the total combinations of the spare rows and the spare columns, the number of the combinations increases with increasing numbers of the bit fails and spares, so that a long remedy processing time is inevitably required. As a result, there exists a problem in that when a device eventually decided as a defective device is tested, the defective device can be decided as being non-remedy (i.e., the remedy is impossible) after all the combinations of the spare rows and the spare columns has been executed.
Further, in general when the remedy solution is obtained for bit fail remedy, it is necessary to select any suitable solution by which the number of used spare lines can be minimized, from among some remedy solutions. In this case, since all the spare combinations must be executed, the number of the spare combinations increases with increasing number of spares, with the result that a long remedy processing time is needed.
In more detail, in the bit fail remedy processing for obtaining one remedy solution, when all the combinations of the remaining spares are allocated and further the remaining bit fail no more exists during the combination processing of the remaining spares, the combination obtained at this time becomes one of the remedy solutions. Here, the number of these combinations increases with increasing number of the remaining rows, increasing number of the spare columns, and increasing number of the remaining bit fails. Therefore, since the non-remedy or the impossible remedy is decided only after all the combination processings have been executed, there exists problems in that the throughput is reduced and further the remedy processing cannot be completed within an FC test time.
Further, in the prior art semiconductor test system, since there exists a tendency that the number of the spares increases with increasing capacity of the memory device, when the wafer is tested by use of the prior art redundancy processor, the capacity of the buffer memory for storing the fail addresses inevitably increases. In addition, when the capacity of the buffer memory increases, since the number of the buffer memory devices increases, there arises another problems in that the number of the substrates thereof increases and the casing of the buffer memory devices is large-sized, with the result that the cost of the buffer memory inevitably increases.
Further, in the prior art test system, the remedy decision processing for the bit fails is executed by allocating usable spares to the fail addresses. In this case, however, since the allocation processing is executed for all the combinations of the row spares and the column spares, there exists the other problem in that the number of the allocation combinations increases and thereby the processing time inevitably increases with increasing number of the spares.